The present invention relates to power supplies, and more particularly, to a power supply detection device for an integrated circuit using at least two power supply voltages. One power supply voltage is for a core of the integrated circuit, which is defined by the manufacturing technology of the circuit. The other power supply voltage is a voltage greater than the power supply voltage for the core, and is applied to external interfaces of the integrated circuit and to input/output interface circuits within the integrated circuit.
Integrated circuits with a distinct core supply voltage and a distinct interface supply voltage have appeared with new manufacturing technologies used to make low-voltage integrated circuits. For these circuits, the core voltage has fallen to 1.8 volts in certain technologies (0.18 xcexc) and 1.2 volts in other technologies (0.12 xcexc).
Since these circuits have to be used in systems whose power supply voltage is higher, the input/output interface circuits include a level-matching stage. For the transmission of output signals, this level matching is carried out by a level translator type selector switch, which receives the interface power supply voltage. This switch matches the levels of the logic signals received from the core of the integrated circuit, and those received from the external circuits with which it exchanges data.
Internal control signals are commonly used to control the interface circuits. Some of these signals also go through the level translators. As for the signals received at input from the integrated circuit, they enter with an interface voltage level. Their level must therefore be lowered.
It has been observed that these input-output interface circuits are the site of malfunctions related either to the disappearance of the core supply voltage, or to the fact that the build-up of this voltage is slower than that of the interface supply voltage. In both situations, the level translators of the interface circuits do not work properly, and malfunctions are seen in the integrated circuit.
It may be recalled that level translators commonly have a structure with two arms, each comprising a control transistor and a load transistor. One of the control transistors is controlled by an input logic signal DATA, and the other is controlled by the inverse logic signal/DATA.
When the core supply voltage disappears, the two logic voltages DATA and /DATA fall to zero. The two control transistors are then off. The voltage at an output of the translator becomes uncontrollable and dependent on the leakage currents in the transistors of the translator, or on a contradiction between two logic signals.
There may then be unnecessary consumption in the interface circuit, related to an untimely operation of a part of the interface circuits. It would be desirable to detect these situations in order to force the output signals of the translators, and therefore the internal control signals and the output signals of the interface circuits, into a defined state. In particular, the most reliable state for the output signals in a core power-off situation is the high impedance state.
A voltage detection device meeting these requirements must furthermore be adapted to various external constraints. The interface supply voltage may indeed have a different level depending on the application. For example, it may be 2.3 volts to 3.6 volts for interfaces covering typical supply voltages of 2.5 volts and 3.5 volts.
The detector must work properly throughout this range of voltage. Furthermore, it should not consume power in the stable states. A classic detector typically comprises an inverter stage controlled by the core supply voltage and powered by the interface supply voltage by a diode or series of diodes.
If, in a given application, the interface supply voltage is within the lower limit, 2.3 volts in the example, there will not be enough voltage to properly power the inverter stage because of the drop in voltage in the diodes. If, in a given application, the interface supply voltage is within the higher limit, 2.6 volts in the example, there will be, on the contrary, excessive voltage so that the inverter will consume power all the time.
In view of the foregoing background, an object of the present invention is to provide a voltage detector that detects unnecessary consumption in the interface circuit while meeting the above described constraints.
The invention therefore relates to a device for the detection of the level of the core supply voltage of an integrated circuit with respect to the level of an interface power supply voltage at a higher nominal level, applied as a power supply voltage to interface circuits of the integrated circuit. For the transmission of input/output signals, the detection device gives a detection signal applied to the interface circuits to set their output in a state of high impedance and minimize their power consumption when the level of the core supply voltage is far too low to enable operation of the integrated circuit.
According to one aspect of the invention, this voltage detection device comprises an input stage comprising an inverter controlled by the core voltage. The input stage is powered with the interface power supply voltage by a power supply stage comprising a diode or series of diodes and a capacitor.
In one variation, the capacitor is formed by a P-type MOS transistor that is series-connected between the diode or series of diodes and the inverter of the input stage. Its gate is then connected to ground and its substrate electrode or well is connected to the interface supply voltage. Its drain and source may also be connected together.
In another alternative embodiment, the detection device furthermore comprises a buffer type output stage comprising an inverter directly powered by the interface power supply voltage and a pull-down transistor for pulling the output node of the inverter of the input stage, controlled by the signal delivered by the output stage, to the interface power supply voltage.
In another alternative embodiment, the detection device comprises a current loop with gain greater than 1 associated with the input stage, and an output stage is connected between the interface power supply voltage and ground. A first transistor copies the current of the loop, and a second translator that is controlled by the core supply voltage is series-connected with the first transistor. The detection signal is given by the intermediate connection node between the first and second transistors. This output signal of the detection device is applied to the input/output interface circuits of the integrated circuit, powered by the interface supply voltage Vdd3, to set them in a high impedance state and minimize their consumption.